1. Field of the Invention
The invention relates to a method of fabricating a high voltage semiconductor, and more particularly to a method of fabricating a lightly doped drain (LDD) in a semiconductor device.
2. Description of the Related Art
The modern integrated circuit techniques is developed towards the direction of narrower line width and shorter channel length of a metal oxide semiconductor (MOS). By applying a constant voltage, the lateral electric field in the channel is increased as reducing the channel length. Thus, the electron in the channel is accelerated, and the energy of the electron is increased, especially in the vicinity between the channel and the source/drain region. The energy of the electron is higher than the energy of an electron under thermal equilibrium. Some of the electron in the channel tunnels through the oxide layer. Therefore, the produced hole flows into the substrate, and a leakage current occurs.
To reduce the hot electron effect, a lightly doping process is performed at the vicinity between the source/drain region and the channel before the formation of a heavily doped source/drain region. An LDD structure is formed, and the leakage current is prevented.
Referring to FIG. 1A to FIG. 1E, cross sectional views of an LDD structure in a MOS is shown.
Referring to FIG. 1A, on a P-type semiconductor substrate 1, an oxide layer 2 is formed. On the oxide layer, a conductive layer 2 is formed. After patterning, a gate 4 is formed. The formation of the oxide layer 2 is to moderate the scattering of subsequent implanted ions due to collision with the silicon atoms of the substrate in an amorphous form. The diffusion of ions into the P-type semiconductor substrate is thus avoided.
Referring to FIG. 1B, N.sup.- ions are implanted with an angle of about 0.degree. to 7.degree. towards the semiconductor substrate 1 to form a lightly doped region 6 and 8. The implantation ions are, for example, phosphorous ions (P.sup.31) having a concentration of 1.times.10.sup.13 /cm.sup.2 to 1.times.10.sup.14 /cm.sup.2 with an energy between 30 KeV to 100 KeV. The resultant implantation depth is about 0.02 .mu.m to 0.15 .mu.m.
Referring to FIG. 1C, using thermal drive-in, the implantation depth of the lightly doped region 6 and 8 is extended from to 0.25 .mu.m to 0.6 .mu.m as a lightly doped region 6a and 8a. The thermal drive-in is performed at about 850.degree. C. to 1050.degree. C.
Referring to FIG. 1D, a silicon oxide layer is formed and defined to form a spacer 10 on s side wall of the gate.
Referring to FIG. 1E , using the gate 2 and the spacer 10 as masks, ion implantation is performed with heavy N.sup.+ ions at an angle of about 0.degree. to 7.degree. to form a heavily doped region 6b and 8b. The implantation ions are, for example, phosphorous or arsenic ions with a concentration of about 1.times.10.sup.14 /cm.sup.2 to 1.times.10.sup.15 /cm.sup.2 at an energy about 100 KeV to 200 KeV.
In the convention method of fabricating a high voltage semiconductor, an LDD source/drain structure is formed after the formation of gate. A lightly ion implantation is performed to form a lightly doped region. By thermal drive-in, the implantation depth of the lightly doped region is extended. After the formation of a spacer, a heavy doped region is formed within the lightly doped region by ion implantation. Using the gate as a mask to perform ion implantation, the concentration of dopant within the gate is altered, and therefore, the characteristics of the device, such as the threshold voltage, are altered. Moreover, during the thermal drive-in process, a cross diffusion occurs between the gate and the lightly doped region. Thus, the device is degraded. The degradation is further obvious for the sub-micron process.